Nonvolatile memory cells having a floating gate for the storage of charges thereon to control the conduction of current in the channel in the substrate of the semiconductive material is well known in the art. See, for example, U.S. Pat. No. 5,029,130 whose disclosure is incorporated herein by reference in its entirety. Structurally, nonvolatile memory cells using a floating gate for storage can be classified as either a stacked gate configuration or a split gate configuration. In a stacked gate, a control gate is positioned directly over the floating gate. In a split gate, the control gate is positioned to one side and controls another portion of the channel along with the floating gate.
Contact-less arrays of floating gate nonvolatile memory cells are also well known in the art. The term “contact-less” means the source lines and the bit lines to the memory cells in the array are buried. Contact-less permits the memory cells to be positioned closer together since contacts or vias do not have to be etched in the semiconductor structure to contact the bit line or the source line. See, for example, U.S. Pat. Nos. 6,420,231 and 6,103,573. These patents disclose a contact-less array of floating gate nonvolatile memory cells but using field oxide to separate rows or columns of memory cells.
In an article entitled “A 1 Gb Multi-Level AG-AND-Type Flash Memory with 10 MB/s Programming Throughput for Mass Storage Application” by Keiichi Yoshida, et. al, published in the 2003 IEEE International Solid State Circuits Conference, Session 16 in 2003, the authors described an array of floating gate nonvolatile memory cells. See also, the paper entitled “10-MB/s Multi-Level Programming of Gb-Scale Flash Memory Enabled by New AG-AND Cell Technology” by Y. Sasago et. al, published in the 2002 IEDM, pp. 952–954.
A cross-sectional view of an array 10 of floating gate nonvolatile memory cells disclosed in the aforementioned paper is shown on FIG. 1A. A schematic diagram of the array 10 is shown in FIG. 1B. The array 10 comprises a plurality memory cells 12 arranged in a plurality of rows and columns. Each memory cell comprises a conventional transistor 11 having a gate 14 and a first terminal 16 and second terminal 18. In addition, the memory cell 12 comprises a stacked gate floating gate transistor 15 having a control gate 24, a floating gate 22, a first terminal 19 connected to the second terminal 18 of the transistor 11 and a second terminal 20. Thus each memory cell 12 has four terminals: a first terminal 16, a second terminal 20, a transistor gate terminal 14 and a control gate terminal 24. Further, as can be seen from FIG. 1B, adjacent memory cells 12 in the same row share a common buried line, which is a buried source line for memory cells to one side, and is a buried bit line for memory cells to another side. In addition, memory cells 12 in the same column have the transistor gates 14 connected together. Thus the buried source lines 20, buried bit lines 16, and the transistor gates 14, all run in the column direction. Finally, memory cells in the same row have their control gates 24 connected to the same row line 30. Further, all of the memory cells 12 are manufactured on a planar surface of a semiconductor substrate.
It is one object of the present invention to increase the density of the array 10 and to provide methods for manufacturing such improved memory cell array.